| PART |
Description |
Maker |
| DM74ALS257 DM74ALS258 DM74ALS257M DM74ALS257N DM74 |
3-STATE Quad 1-of-2 Line Data Selector/Multiplexer (Inverting)
From old datasheet system
2-Input Digital Multiplexer
10-Bit Bus-Interface Flip-Flop With 3-State Outputs 24-TSSOP -40 to 85
3-STATE Quad 1-of-2-Line Data Selector/Multiplexer(1线数据选择多路复用器（三态输出）) 三态四1 - 2 -线数据选择多路（四21线数据选择多路复用器（三态输出）
3-STATE Quad 1-of-2-Line Data Selector/Multiplexer ALS SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDIP16
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor Corporation
Fairchild Semiconductor, Corp.
|
| NB6L56 |
Clock / Data Multiplexer, 2.5 V / 3.3 V Dual 2:1 Differential, with LVPECL Outputs
|
ON Semiconductor
|
| DM74LS151 DM74LS151M DM74LS151N DM74LS151SJ 74LS15 |
8-Input Digital Multiplexer
1-of-8 Line Data Selector/Multiplexer
|
Fairchild Semiconductor Corporation
FAIRCHILD[Fairchild Semiconductor]
|
| TTRN012G73XE1 TTRN012G5 TTRN012G53XE1 TTRN012G7 |
TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer
|
AGERE[Agere Systems]
|
| ADN2819ACPZ-CML-RL1 ADN2819ACP-CML ADN2819 EVAL-AD |
Multi Rate Limiting Amplifier and Clock and Data Recovery ICs
Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
N/A
|
AD[Analog Devices]
|
| DM74S253 DM74S253N |
Dual 3-STATE 1-of-4 Line Data Selector/Multiplexer S SERIES, DUAL 4 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16
From old datasheet system
|
Fairchild Semiconductor, Corp.
FAIRCHILD[Fairchild Semiconductor]
|
| HCF40257 HCF40257BEY HCF40257BM1 HCF40257M013TR |
4000/14000/40000 SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDIP16
4000/14000/40000 SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16
QUAD 2-LINE-TO-1-LINE DATA SELECTOR/MULTIPLEXER
QUAD 2-LINE-TO-1-LINE DATA SELECTOR/MULTIPLEXER
|
STMicroelectronics
ST Microelectronics
|
| M13S5121632A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M14D2561616A-2E |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| W9412G6JH W9412G6JH-5 |
2M ?4 BANKS ?16 BITS DDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
|
Winbond
|
